AlexandreSinger

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active 2023-09-04 → 2026-09-25 (UTC) · 30 repositories

Complete coverage27,305 / 27,308 hourly files (100%) · 2 absent upstream2023-08-15 → 2026-09-25 (UTC)

Events

4.3K

Pushes

1.5K

Pull requests

476

Issues

Reviews

500

Repositories

Activity over time

Daily event counts in the loaded window

Pushes
Pull requests
Issues

Pull requests and issues are under-captured in the later part of this window. GH Archive progressively stopped recording non-push events during 2026 — −95% or worse by the end of the window. A decline in those two series reflects the archive rather than this account. Pushes stay reliable throughout, so read them as the real signal. Data health has the measurements.

Repositories worked on

Ranked by contributions — pushes, PRs, issues, reviews and comments, so stars and forks do not inflate the list

Repository	Contributions	Pushes	PRs	Issues	Comments	Last seen
verilog-to-routing/vtr-verilog-to-routing	2,179	371	338	64	952	2026-09-25
AlexandreSinger/vtr-verilog-to-routing	858	732	26	0	74	2026-08-10
AlexandreSinger/rust-fpga-arch-visualizer	210	117	76	13	4	2026-06-21
verilog-to-routing/libsdcparse	85	69	4	0	9	2026-06-02
AlexandreSinger/fpga-analytical-placement	78	46	11	0	11	2026-07-20
siliconcompiler/siliconcompiler	49	31	7	0	9	2025-09-05
AlexandreSinger/fine-grained-parallel-router	32	32	0	0	0	2025-06-23
AlexandreSinger/fpga-timing-benchmarks	19	13	4	0	1	2025-11-19
siliconcompiler/fpga-timing-coverage-suite	14	5	5	0	2	2026-03-09
Huawei-PTLab/PyDSL	11	11	0	0	0	2024-02-02
StephenMoreOSU/rad_gen	11	0	0	0	9	2024-07-26
AlexandreSinger/mlir-beginner-friendly-tutorial	10	10	0	0	0	2025-03-11
verilog-to-routing/ezgl	9	5	2	0	2	2026-06-19
AlexandreSinger/mlir-beginner-friendly-tutorial-2	4	4	0	0	0	2026-07-17
verilog-to-routing/tatum	3	1	1	1	0	2026-04-08
AlexandreSinger/dotfiles	2	2	0	0	0	2025-03-15
RonZ13/vtr-verilog-to-routing	2	2	0	0	0	2025-05-14
AlexandreSinger/uxsdcxx	1	1	0	0	0	2025-11-30
SymbiFlow/uxsdcxx	1	0	1	0	0	2024-11-30
verilog-to-routing/verilog-to-routing.github.io	1	0	1	0	0	2026-04-08
heshpdx/vtr-verilog-to-routing	1	1	0	0	0	2024-09-17
trick2011/vtr-verilog-to-routing	1	1	0	0	0	2024-07-16
ueqri/vtr-verilog-to-routing	1	1	0	0	0	2025-03-10
w0lek/vtr-verilog-to-routing	1	1	0	0	0	2024-09-21
markram1729/vtr-verilog-to-routing	1	1	0	0	0	2025-02-23
AlexandreSinger/tatum	1	1	0	0	0	2024-05-28
nbstrong/vtr-verilog-to-routing	1	1	0	0	0	2024-07-16
amin1377/vpr_scripts	0	0	0	0	0	2024-03-27
AlexandreSinger/SavableAudio	0	0	0	0	0	2024-02-05
gaofangfrank/dotfiles	0	0	0	0	0	2024-03-29

Works with

People who contribute to the same repositories, ranked by how many they share · automation excluded, or every account would appear to work with everyone

Contributor	Shared repos	Repositories in common
vaughnbetz	6	ueqri/vtr-verilog-to-routing verilog-to-routing/verilog-to-routing.github.io verilog-to-routing/libsdcparse verilog-to-routing/vtr-verilog-to-routing+2
robluo	4	verilog-to-routing/vtr-verilog-to-routing AlexandreSinger/fpga-analytical-placement StephenMoreOSU/rad_gen AlexandreSinger/vtr-verilog-to-routing
ueqri	4	verilog-to-routing/vtr-verilog-to-routing AlexandreSinger/fine-grained-parallel-router ueqri/vtr-verilog-to-routing AlexandreSinger/vtr-verilog-to-routing
AmirhosseinPoolad	3	verilog-to-routing/libsdcparse verilog-to-routing/vtr-verilog-to-routing verilog-to-routing/ezgl
StephenMoreOSU	3	verilog-to-routing/vtr-verilog-to-routing siliconcompiler/siliconcompiler StephenMoreOSU/rad_gen
petergrossmann21	3	verilog-to-routing/libsdcparse siliconcompiler/siliconcompiler verilog-to-routing/vtr-verilog-to-routing
w0lek	3	verilog-to-routing/vtr-verilog-to-routing w0lek/vtr-verilog-to-routing verilog-to-routing/ezgl
AllenDBoston	2	verilog-to-routing/vtr-verilog-to-routing siliconcompiler/siliconcompiler
Minchan-Kwon	2	siliconcompiler/fpga-timing-coverage-suite AlexandreSinger/fpga-timing-benchmarks
RonZ13	2	verilog-to-routing/vtr-verilog-to-routing RonZ13/vtr-verilog-to-routing
coolbreeze413	2	verilog-to-routing/libsdcparse verilog-to-routing/vtr-verilog-to-routing
duck2	2	verilog-to-routing/vtr-verilog-to-routing SymbiFlow/uxsdcxx
gigeresk	2	verilog-to-routing/vtr-verilog-to-routing siliconcompiler/siliconcompiler
heshpdx	2	verilog-to-routing/vtr-verilog-to-routing heshpdx/vtr-verilog-to-routing
kevinxing-a12	2	verilog-to-routing/vtr-verilog-to-routing verilog-to-routing/ezgl
markram1729	2	verilog-to-routing/vtr-verilog-to-routing markram1729/vtr-verilog-to-routing
nedsels	2	verilog-to-routing/vtr-verilog-to-routing AlexandreSinger/vtr-verilog-to-routing
AlexPoupakis	1	verilog-to-routing/vtr-verilog-to-routing
Andrea-Spitale	1	siliconcompiler/siliconcompiler
Blebowski	1	siliconcompiler/siliconcompiler
CimboAkinci	1	verilog-to-routing/vtr-verilog-to-routing
Ciprian167	1	siliconcompiler/siliconcompiler
DuqingF	1	verilog-to-routing/vtr-verilog-to-routing
E00N777	1	AlexandreSinger/mlir-beginner-friendly-tutorial
GabrielAguirre1	1	siliconcompiler/siliconcompiler

Counts cover only the window loaded into ClickHouse and count events, not this account's lifetime totals on GitHub.