ArunkumarK07

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active 2024-02-20 → 2025-11-12 (UTC) · 43 repositories

Complete coverage26,602 / 26,602 hourly files (100%) · 2 absent upstream2023-08-15 → 2026-08-27 (UTC)

Events

163

Pushes

105

Pull requests

Issues

Reviews

Repositories

Activity over time

Daily event counts in the loaded window

Pushes
Pull requests
Issues

Pull requests and issues are under-captured in the later part of this window. GH Archive progressively stopped recording non-push events during 2026 — −95% or worse by the end of the window. A decline in those two series reflects the archive rather than this account. Pushes stay reliable throughout, so read them as the real signal. Data health has the measurements.

Repositories worked on

Ranked by contributions — pushes, PRs, issues, reviews and comments, so stars and forks do not inflate the list

Repository	Contributions	Pushes	PRs	Last seen
ArunkumarK07/Design-Implementation-of-2-Bit-Multiplier-using-Cadence-Tools	10	10	0	2025-05-15
ArunkumarK07/Design-Implementation-of-1-Bit-Full-Adder-using-Cadence-Tools	9	8	1	2025-10-05
ArunkumarK07/Design-Implementation-of-6T---SRAM-Cell-using-Cadence-EDA-Tools	9	9	0	2025-08-28
ArunkumarK07/Design-and-Simulation-of-a-4-Bit-Adder-Using-cadence-nclaunch	9	9	0	2025-10-28
ArunkumarK07/EXP1-Design-Implementation-of-CMOS-Inverter-Design-using-Cadence-EDA-Tool	7	7	0	2025-03-28
ArunkumarK07/Multiplexer-Simulation-in-Vivado	6	6	0	2025-03-15
ArunkumarK07/ALU-DESIGN_System-Verilog-	6	6	0	2025-09-16
ArunkumarK07/Implementation-Analysis-of-D-flipflop-using-Cadence-EDA-Tools	5	5	0	2025-03-28
ArunkumarK07/Design-and-Simulation-of-a-Booth-Multiplier-Using-Verilog-and-Cadence-nclaunch	5	5	0	2025-05-21
ArunkumarK07/EXP02--Design-Implementation-of-Full-Custom-2-1-MUX-using-Cadence-EDA-Tools	4	4	0	2025-10-05
ArunkumarK07/Seven-segment-display-using-Verilog-HDL-	4	4	0	2025-03-15
ArunkumarK07/seven-segment-display-using-Verilog-HDL-	4	3	1	2025-09-17
ArunkumarK07/Flipflop-using-blocking-assignment	3	3	0	2025-09-17
ArunkumarK07/2-1-MUX-Implementation-in-Spartan-7-FPGA	3	3	0	2025-11-12
ArunkumarK07/APB-Packet-Modeling-using-SystemVerilog-OOP	2	2	0	2025-09-16
ArunkumarK07/Design-a-Calculator-using-Cadence-Tools	2	2	0	2024-10-19
ArunkumarK07/8-to-1-Multiplexer-System-Verilog	2	2	0	2025-09-16
ArunkumarK07/Verilog-Task-and-Function-Example	2	2	0	2025-11-12
ArunkumarK07/Simulation-of-Sequence-Detector-Using-Mealy-Machine-in-Verilog-HDL	2	2	0	2025-11-12
ArunkumarK07/Design-and-Simulation-of-a-4-Bit-Adder-Using-Verilog-and-Cadence-Genus	1	1	0	2025-03-28
ArunkumarK07/Traffic-Light-Controller-Using-Verilog-HDL	1	1	0	2024-10-04
ArunkumarK07/KB-ROM-Memory-with-Read-and-Write-Operations-	1	1	0	2024-10-08
ArunkumarK07/Sequence-Detector	1	1	0	2024-10-08
ArunkumarK07/Swapping-of-three-numbers-using-Verilog-HDL-	1	1	0	2024-09-19
ArunkumarK07/Verilog-Code-for-Swapping-Three-Numbers	1	1	0	2024-10-04
ArunkumarK07/Interface-Design-for-DUT-Ports-and-Signal-Encapsulation	1	1	0	2025-11-03
ArunkumarK07/RAM-ROM-FIFO-in-Verilog-HDL	1	1	0	2025-11-12
ArunkumarK07/Assertion-Based-Verification-of-I-C-Protocol-Timing-and-Handshaking-Sequences-	1	1	0	2025-11-03
ArunkumarK07/Flipflops-using-Non-blocking-assignmnet	1	1	0	2025-09-23
ArunkumarK07/Design-and-Verification-of-Register-Memory-Access-using-Mailbox-based-Producer-Consumer-Model	1	1	0	2025-11-03
ArunkumarK07/4-KB-ROM-Memory-with-Read-and-Write-Operations	1	1	0	2024-10-08
ArunkumarK07/4_1_Multiplexer-Simulation-in-Vivado	1	1	0	2025-09-17
ArunkumarK07/HDL-Programs	0	0	0	2025-03-29
ArunkumarK07/Python-Basic-Programs	0	0	0	2024-07-19
ArunkumarK07/CADENCE-EXPERIMENTS	0	0	0	2024-08-16
ArunkumarK07/Design-and-Simulation-of-a-Booth-Multiplier-Using-Verilog-and-Cadence-Genus	0	0	0	2025-03-28
ArunkumarK07/4-bit-Ripple-Carry-Adder-using-Task-and-4-bit-Ripple-Counter-using-Function-with-Testbench	0	0	0	2024-11-12
Digilent/vivado-library	0	0	0	2025-03-16
vipinkmenon/SpatialFilter	0	0	0	2025-03-18
ArunkumarK07/Functional-Verification-of-Asynchronous-FIFO	0	0	0	2025-11-03
ArunkumarK07/8to1-multiplexer-systemverilog	0	0	0	2025-09-16
ArunkumarK07/MUX-Implementation-in-Spartan-7-FPGA	0	0	0	2025-11-12
ArunkumarK07/Sequence-Detector-Using-Moore-Machine	0	0	0	2025-11-12

Works with

People who contribute to the same repositories, ranked by how many they share · automation excluded, or every account would appear to work with everyone

Contributor	Shared repos	Repositories in common
cool-user-04	6	ArunkumarK07/Sequence-Detector ArunkumarK07/4-KB-ROM-Memory-with-Read-and-Write-Operations ArunkumarK07/Seven-segment-display-using-Verilog-HDL-ArunkumarK07/Multiplexer-Simulation-in-Vivado+2
HariharanGanesh	5	ArunkumarK07/Design-and-Simulation-of-a-4-Bit-Adder-Using-cadence-nclaunch ArunkumarK07/Implementation-Analysis-of-D-flipflop-using-Cadence-EDA-Tools ArunkumarK07/EXP02--Design-Implementation-of-Full-Custom-2-1-MUX-using-Cadence-EDA-Tools ArunkumarK07/Design-Implementation-of-2-Bit-Multiplier-using-Cadence-Tools+1
AJAYD313	4	ArunkumarK07/EXP1-Design-Implementation-of-CMOS-Inverter-Design-using-Cadence-EDA-Tool ArunkumarK07/EXP02--Design-Implementation-of-Full-Custom-2-1-MUX-using-Cadence-EDA-Tools ArunkumarK07/Implementation-Analysis-of-D-flipflop-using-Cadence-EDA-Tools ArunkumarK07/Design-Implementation-of-6T---SRAM-Cell-using-Cadence-EDA-Tools
DHANUSH-G11	3	ArunkumarK07/Traffic-Light-Controller-Using-Verilog-HDL ArunkumarK07/Seven-segment-display-using-Verilog-HDL-ArunkumarK07/Verilog-Code-for-Swapping-Three-Numbers
Vishal-614	2	ArunkumarK07/Traffic-Light-Controller-Using-Verilog-HDL ArunkumarK07/Verilog-Code-for-Swapping-Three-Numbers
jayasankar2007	2	ArunkumarK07/Implementation-Analysis-of-D-flipflop-using-Cadence-EDA-Tools ArunkumarK07/Design-and-Simulation-of-a-Booth-Multiplier-Using-Verilog-and-Cadence-nclaunch
prakaxh02	2	ArunkumarK07/EXP1-Design-Implementation-of-CMOS-Inverter-Design-using-Cadence-EDA-Tool ArunkumarK07/EXP02--Design-Implementation-of-Full-Custom-2-1-MUX-using-Cadence-EDA-Tools
ugendran444	2	ArunkumarK07/EXP1-Design-Implementation-of-CMOS-Inverter-Design-using-Cadence-EDA-Tool ArunkumarK07/EXP02--Design-Implementation-of-Full-Custom-2-1-MUX-using-Cadence-EDA-Tools
vishalsudhakar04	2	ArunkumarK07/Flipflops-using-Non-blocking-assignmnet ArunkumarK07/Flipflop-using-blocking-assignment
Akshaya6832	1	ArunkumarK07/Implementation-Analysis-of-D-flipflop-using-Cadence-EDA-Tools
CalebSamraj14	1	ArunkumarK07/4-KB-ROM-Memory-with-Read-and-Write-Operations
DHARSHINIA-ENG	1	ArunkumarK07/4_1_Multiplexer-Simulation-in-Vivado
Dhayanithi2005	1	ArunkumarK07/Design-Implementation-of-1-Bit-Full-Adder-using-Cadence-Tools
Elakkiya256	1	ArunkumarK07/EXP1-Design-Implementation-of-CMOS-Inverter-Design-using-Cadence-EDA-Tool
Jayavishal9894	1	ArunkumarK07/Multiplexer-Simulation-in-Vivado
MANODEEPAN11	1	ArunkumarK07/EXP02--Design-Implementation-of-Full-Custom-2-1-MUX-using-Cadence-EDA-Tools
Mahadeva630	1	ArunkumarK07/Implementation-Analysis-of-D-flipflop-using-Cadence-EDA-Tools
Mithunmv134	1	ArunkumarK07/4-KB-ROM-Memory-with-Read-and-Write-Operations
MohammedMunavarBasha	1	ArunkumarK07/Design-and-Simulation-of-a-Booth-Multiplier-Using-Verilog-and-Cadence-nclaunch
NANDAVELAN	1	ArunkumarK07/EXP1-Design-Implementation-of-CMOS-Inverter-Design-using-Cadence-EDA-Tool
Nisargapriya	1	ArunkumarK07/Flipflop-using-blocking-assignment
Pradeepkumarsec	1	ArunkumarK07/Implementation-Analysis-of-D-flipflop-using-Cadence-EDA-Tools
Prasathweb	1	ArunkumarK07/Traffic-Light-Controller-Using-Verilog-HDL
Rakshan1609	1	ArunkumarK07/EXP02--Design-Implementation-of-Full-Custom-2-1-MUX-using-Cadence-EDA-Tools
Vishnu2005-ops	1	ArunkumarK07/Implementation-Analysis-of-D-flipflop-using-Cadence-EDA-Tools

Counts cover only the window loaded into ClickHouse and count events, not this account's lifetime totals on GitHub.