wissygh

active 2023-09-01 → 2026-08-12 (UTC) · 34 repositories

Partial coverage20,528 / 26,284 hourly files (78%) · 2 absent upstream · 5,753 failed, retryable2023-08-15 → 2026-08-14 (UTC)— sampled evenly across the window, so rankings and trends hold; absolute counts scale up.

Events

623

Pushes

308

Pull requests

112

Issues

Reviews

Repositories

Activity over time

Daily event counts in the loaded window

Pushes
Pull requests
Issues

Pull requests and issues are under-captured in the later part of this window. GH Archive progressively stopped recording non-push events during 2026 — −95% or worse by the end of the window. A decline in those two series reflects the archive rather than this account. Pushes stay reliable throughout, so read them as the real signal. Data health has the measurements.

Repositories worked on

Ranked by contributions — pushes, PRs, issues, reviews and comments, so stars and forks do not inflate the list

Repository	Contributions	Pushes	PRs	Issues	Comments	Last seen
OpenXiangShan/XiangShan	211	120	64	2	9	2026-08-12
wissygh/XiangShan	65	65	0	0	0	2025-11-27
OpenXiangShan/NEMU	60	38	20	0	1	2026-07-13
wissygh/YunSuan	41	41	0	0	0	2024-04-07
OpenXiangShan/ready-to-run	23	15	8	0	0	2026-07-17
OpenXiangShan/YunSuan	16	4	8	0	0	2026-01-29
wissygh/NEMU	13	13	0	0	0	2026-06-17
OpenXiangShan/rocket-chip	12	4	6	0	1	2026-03-02
OpenXiangShan/riscv-isa-sim	4	1	3	0	0	2026-01-21
riscv-software-src/riscv-isa-sim	4	0	0	0	4	2025-03-19
chipsalliance/rocket-chip	3	0	3	0	0	2025-06-13
OpenXiangShan/riscv-tests	2	2	0	0	0	2024-10-17
wissygh/riscv-tests	2	2	0	0	0	2024-05-30
riscv/riscv-aia	2	0	0	1	1	2024-06-17
riscv/riscv-debug-spec	2	0	0	0	2	2023-12-09
OpenXiangShan/difftest	1	1	0	0	0	2024-07-18
wissygh/riscv-isa-sim	1	1	0	0	0	2025-12-27
riscv-collab/riscv-openocd	1	0	0	1	0	2025-12-24
OpenXiangShan/CoupledL2	1	1	0	0	0	2026-03-20
TapXWorld/ChinaTextbook	0	0	0	0	0	2025-08-07
pulp-platform/ara	0	0	0	0	0	2025-05-26
Anduin2017/HowToCook	0	0	0	0	0	2023-10-23
OpenXiangShan/ChiselAIA	0	0	0	0	0	2025-04-12
f0rm2l1n/riscv-simulator-guide	0	0	0	0	0	2024-01-26
OpenXiangShan/nexus-am	0	0	0	0	0	2023-10-30
pulp-platform/riscv-dbg	0	0	0	0	0	2024-01-24
pulp-platform/pulp_cluster	0	0	0	0	0	2025-01-20
openhwgroup/force-riscv	0	0	0	0	0	2024-03-07
zhenyu-zang/xv6-riscv-book-Chinese	0	0	0	0	0	2024-08-18
riscv-non-isa/tg-nexus-trace	0	0	0	0	0	2024-03-07
openhwgroup/cv32e40p	0	0	0	0	0	2024-01-24
Yatekii/jep106	0	0	0	0	0	2025-07-08
LC044/WeChatMsg	0	0	0	0	0	2023-12-06
qemu/qemu	0	0	0	0	0	2024-06-15

Works with

People who contribute to the same repositories, ranked by how many they share · automation excluded, or every account would appear to work with everyone

Contributor	Shared repos	Repositories in common
poemonsense	10	OpenXiangShan/rocket-chip OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim+6
sinceforYy	10	OpenXiangShan/rocket-chip OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim+6
NewPaulWalker	9	OpenXiangShan/rocket-chip OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim+5
Tang-Haojin	9	OpenXiangShan/rocket-chip OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim+5
cyyself	9	OpenXiangShan/rocket-chip OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim+5
lewislzh	9	OpenXiangShan/rocket-chip OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim+5
huxuan0307	7	OpenXiangShan/rocket-chip OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim+3
Siudya	6	OpenXiangShan/rocket-chip OpenXiangShan/difftest riscv-software-src/riscv-isa-sim OpenXiangShan/CoupledL2+2
good-circle	6	OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim OpenXiangShan/CoupledL2+2
happy-lx	6	OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/CoupledL2 OpenXiangShan/riscv-tests+2
Anzooooo	5	OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim OpenXiangShan/NEMU+1
Copilot	5	OpenXiangShan/difftest riscv-software-src/riscv-isa-sim OpenXiangShan/CoupledL2 OpenXiangShan/NEMU+1
Maxpicca-Li	5	OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim OpenXiangShan/CoupledL2 OpenXiangShan/NEMU+1
Ziyue-Zhang	5	OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/NEMU OpenXiangShan/YunSuan+1
cebarobot	5	OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim OpenXiangShan/NEMU+1
ha0lyu	5	OpenXiangShan/difftest riscv-software-src/riscv-isa-sim chipsalliance/rocket-chip OpenXiangShan/NEMU+1
linjuanZ	5	OpenXiangShan/rocket-chip OpenXiangShan/difftest OpenXiangShan/CoupledL2 OpenXiangShan/NEMU+1
shinezyy	5	OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim OpenXiangShan/NEMU+1
wakafa1	5	OpenXiangShan/ready-to-run OpenXiangShan/difftest OpenXiangShan/CoupledL2 OpenXiangShan/NEMU+1
Emin017	4	OpenXiangShan/difftest chipsalliance/rocket-chip OpenXiangShan/XiangShan OpenXiangShan/CoupledL2
Lemover	4	OpenXiangShan/difftest OpenXiangShan/riscv-isa-sim OpenXiangShan/XiangShan OpenXiangShan/NEMU
TheKiteRunner24	4	OpenXiangShan/rocket-chip OpenXiangShan/XiangShan OpenXiangShan/NEMU OpenXiangShan/CoupledL2
aswaterman	4	riscv/riscv-aia chipsalliance/rocket-chip riscv-software-src/riscv-isa-sim riscv/riscv-debug-spec
cailuoshan	4	OpenXiangShan/difftest OpenXiangShan/XiangShan OpenXiangShan/CoupledL2 OpenXiangShan/NEMU
chenguokai	4	OpenXiangShan/rocket-chip chipsalliance/rocket-chip OpenXiangShan/XiangShan OpenXiangShan/NEMU

Counts cover only the window loaded into ClickHouse and count events, not this account's lifetime totals on GitHub.