youngar

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active 2023-08-15 → 2026-07-21 (UTC) · 13 repositories

Complete coverage27,359 / 27,359 hourly files (100%) · 2 absent upstream2023-08-15 → 2026-09-27 (UTC)

Events

1.1K

Pushes

339

Pull requests

178

Issues

Reviews

187

Repositories

Activity over time

Daily event counts in the loaded window

Pushes
Pull requests
Issues

Pull requests and issues are under-captured in the later part of this window. GH Archive progressively stopped recording non-push events during 2026 — −95% or worse by the end of the window. A decline in those two series reflects the archive rather than this account. Pushes stay reliable throughout, so read them as the real signal. Data health has the measurements.

Repositories worked on

Ranked by contributions — pushes, PRs, issues, reviews and comments, so stars and forks do not inflate the list

Repository	Contributions	Pushes	PRs	Issues	Comments	Last seen
llvm/circt	691	94	172	51	189	2026-04-21
youngar/circt	211	211	0	0	0	2026-07-21
youngar/hwml-rs	30	29	1	0	0	2026-03-26
riscv-non-isa/riscv-arch-test	4	0	4	0	0	2025-12-04
youngar/riscv-arch-test	3	3	0	0	0	2025-12-05
llvm/llvm-project	3	0	0	2	1	2024-11-04
riscv-software-src/riscv-isa-sim	2	0	1	0	1	2025-07-30
sifive/riscv-isa-sim-lib-demo	2	1	0	0	0	2025-05-28
chipsalliance/chisel	2	0	0	0	1	2024-06-18
youngar/litmus-tests-riscv	1	1	0	0	0	2025-04-10
rwy7/circt	0	0	0	0	0	2024-07-19
youngar/riscv-isa-sim	0	0	0	0	0	2025-07-30
litmus-tests/litmus-tests-riscv	0	0	0	0	0	2025-03-08

Works with

People who contribute to the same repositories, ranked by how many they share · automation excluded, or every account would appear to work with everyone

Contributor	Shared repos	Repositories in common
aswaterman	4	riscv-non-isa/riscv-arch-test llvm/llvm-project riscv-software-src/riscv-isa-sim chipsalliance/chisel
nibrunieAtSi5	4	riscv-non-isa/riscv-arch-test llvm/llvm-project riscv-software-src/riscv-isa-sim chipsalliance/chisel
poemonsense	4	llvm/circt llvm/llvm-project riscv-software-src/riscv-isa-sim chipsalliance/chisel
sequencer	4	llvm/circt llvm/llvm-project riscv-software-src/riscv-isa-sim chipsalliance/chisel
unlsycn	4	llvm/circt llvm/llvm-project riscv-software-src/riscv-isa-sim chipsalliance/chisel
CSharperMantle	3	llvm/circt llvm/llvm-project chipsalliance/chisel
Clo91eaf	3	llvm/circt llvm/llvm-project riscv-software-src/riscv-isa-sim
GeorgeLyon	3	llvm/circt llvm/llvm-project chipsalliance/chisel
SpriteOvO	3	llvm/circt llvm/llvm-project chipsalliance/chisel
Tang-Haojin	3	llvm/circt llvm/llvm-project chipsalliance/chisel
Timmmm	3	riscv-non-isa/riscv-arch-test llvm/llvm-project riscv-software-src/riscv-isa-sim
cmuellner	3	riscv-non-isa/riscv-arch-test llvm/llvm-project riscv-software-src/riscv-isa-sim
cyyself	3	llvm/llvm-project riscv-software-src/riscv-isa-sim chipsalliance/chisel
davidharrishmc	3	riscv-non-isa/riscv-arch-test llvm/llvm-project riscv-software-src/riscv-isa-sim
dtzSiFive	3	llvm/circt llvm/llvm-project chipsalliance/chisel
fabianschuiki	3	llvm/circt llvm/llvm-project chipsalliance/chisel
fanghuaqi	3	riscv-non-isa/riscv-arch-test llvm/llvm-project riscv-software-src/riscv-isa-sim
jerryz123	3	llvm/circt riscv-software-src/riscv-isa-sim chipsalliance/chisel
maerhart	3	llvm/circt llvm/llvm-project chipsalliance/chisel
mikeurbach	3	llvm/circt llvm/llvm-project chipsalliance/chisel
nandor	3	llvm/circt llvm/llvm-project chipsalliance/chisel
rwy7	3	llvm/circt youngar/hwml-rs chipsalliance/chisel
seldridge	3	llvm/circt llvm/llvm-project chipsalliance/chisel
trdthg	3	riscv-non-isa/riscv-arch-test llvm/llvm-project riscv-software-src/riscv-isa-sim
trmckay	3	llvm/circt llvm/llvm-project chipsalliance/chisel

Counts cover only the window loaded into ClickHouse and count events, not this account's lifetime totals on GitHub.