This processor is designed to support the RISC-V architecture and can handle instructions from the RV32I instruction set, including add, sub, or, and, sll, lw, addi, sw, beq, and jal. An example program has been initially loaded into the instruction memory of the processor.
active 2024-12-07 → 2024-12-07 (UTC)
Activity over time
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Line chart, 1 days from 2024-12-07 to 2024-12-07. Pushes: 0 total, peak 0 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.
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Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
Nobody pushed, opened or commented here in the loaded window — this repo's activity is stars and forks only.
Recent activity
Latest issues, pull requests and releases
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Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.