This project involves designing and implementing a 32-bit processor using Verilog Hardware Description Language (HDL). The processor is created as part of this NIELIT Internship, as an effort to understand the basics of computer architecture and digital design.
active 2024-10-14 → 2024-10-15 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 2 days from 2024-10-14 to 2024-10-15. Pushes: 6 total, peak 5 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| AdityaMino | 6 | 6 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.