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Anish-Rooj-cpu/Single-Cycle-RISCV-Processor-using-Verilog-HDL

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In this project I have designed a Single Cycle RISCV Processor using Verilog HDL

active 2025-06-12 → 2025-07-04 (UTC)

Partial coverage13,307 / 15,836 hourly files (84%) · 2 absent upstream · 2,523 failed, retryable2024-10-20 → 2026-08-11 (UTC)— sampled evenly across the window, so rankings and trends hold; absolute counts scale up.
Events
21
Pushes
13
Pull requests
0
Issues
0
Stars
6
Forks
0

Activity over time

Daily event counts in the loaded window

Line chart, 23 days from 2025-06-12 to 2025-07-04. Pushes: 13 total, peak 10 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 6 total, peak 3 in a day.

  • Pushes
  • Pull requests
  • Issues
  • Comments
  • Stars

Top contributors

Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity

ContributorContributionsPushesPRsComments
Anish-Rooj-cpu131300

Recent activity

Latest issues, pull requests and releases

No issue or PR events — this repo's activity is pushes only.

Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 6 stars here means stars gained during the window, not the repo's star count.