This VHDL project is a basic 19-bit ALU that performs arithmetic (ADD, SUB, MUL, DIV) and logic (AND, OR, XOR, NOT) operations based on a 4-bit control signal. It outputs the result and can also set a zero flag to indicate when the result is zero.
active 2024-09-23 → 2024-09-23 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 1 days from 2024-09-23 to 2024-09-23. Pushes: 1 total, peak 1 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| Arjun54325 | 1 | 1 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.