A custom 32-bit RISC processor implemented in Verilog, demonstrating datapath, control logic, and instruction execution.
active 2026-01-22 → 2026-02-06 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 16 days from 2026-01-22 to 2026-02-06. Pushes: 17 total, peak 7 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 18 total, peak 6 in a day. Comments: 0 total, peak 0 in a day. Stars: 1 total, peak 1 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Stars, PRs, issues and forks are under-captured in the later part of this window. GH Archive progressively stopped capturing non-push events during 2026 — −95% or worse by the end of the window. Every series here except Pushes fades for that reason, so a decline above reflects the archive, not this repository. Pushes stay reliable throughout, so read them, and the contributor counts derived from them, as the real signal. Data health has the measurements.
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| ArjunPShetty | 32 | 17 | 0 | 0 |
| varshinipshetty | 2 | 0 | 0 | 0 |
| Preetham404 | 1 | 0 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
- Issue#19ArjunPShetty2026-01-25 14:27Branch Prediction Always-Not-Taken
- Issue#19ArjunPShetty2026-01-25 14:27Branch Prediction Always-Not-Taken
- Issue#20ArjunPShetty2026-01-25 14:25Add Simple Instruction Cache
- Issue#20ArjunPShetty2026-01-25 14:25Add Simple Instruction Cache
- Issue#19varshinipshetty2026-01-25 14:24Branch Prediction Always-Not-Taken
- Issue#14ArjunPShetty2026-01-25 02:32ALU Result Always Zero
- Issue#17varshinipshetty2026-01-24 16:46Instruction Memory Not Initialized Properly
- Issue#15ArjunPShetty2026-01-24 07:34ReadData Always X
- Issue#14ArjunPShetty2026-01-24 07:33ALU Result Always Zero
- Issue#14ArjunPShetty2026-01-24 07:33ALU Result Always Zero
- Issue#15ArjunPShetty2026-01-24 07:28ReadData Always X
- Issue#11ArjunPShetty2026-01-24 06:34Write a Simple ALU Testbench
- Issue#9ArjunPShetty2026-01-23 11:03Define Baseline Single-Cycle CPU and Roadmap to Pipelined Architecture
- Issue#7Preetham4042026-01-23 10:53Bare-Metal Hello World Test
- Issue#6ArjunPShetty2026-01-23 10:50Write Architecture Specification
- Issue#6ArjunPShetty2026-01-23 10:50Write Architecture Specification
- Issue#3ArjunPShetty2026-01-23 10:44Implement Instruction Fetch (IF) Stage
- Issue#2ArjunPShetty2026-01-22 16:47ALU Decoder / Control Unit Logic Issues and RTL Cleanup Required
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 1 stars here means stars gained during the window, not the repo's star count.