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DFiant HDL (DFHDL): A Mutli-abstraction Hardware Descripition Language and Framework

active 2024-05-022026-08-15 (UTC)

Complete coverage26,373 / 26,373 hourly files (100%) · 2 absent upstream2023-08-152026-08-17 (UTC)
Events
1.2K
Pushes
601
Pull requests
311
Issues
45
Stars
26
Forks
2

Activity over time

Daily event counts in the loaded window

Line chart, 836 days from 2024-05-02 to 2026-08-15. Pushes: 601 total, peak 27 in a day. Pull requests: 311 total, peak 10 in a day. Issues: 45 total, peak 6 in a day. Comments: 48 total, peak 4 in a day. Stars: 26 total, peak 2 in a day.

  • Pushes
  • Pull requests
  • Issues
  • Comments
  • Stars

Stars, PRs, issues and forks are under-captured in the later part of this window. GH Archive progressively stopped capturing non-push events during 2026 — −95% or worse by the end of the window. Every series here except Pushes fades for that reason, so a decline above reflects the archive, not this repository. Pushes stay reliable throughout, so read them, and the contributor counts derived from them, as the real signal. Data health has the measurements.

Top contributors

Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity

ContributorContributionsPushesPRsComments
soronpo84259719223
scala-steward138011721
MartinC4519004
jchyb1010
github-actions[bot]1100

Recent activity

Latest issues, pull requests and releases

  • Pull request#460scala-steward2026-08-07 17:10
  • Issue comment#448soronpo2026-08-07 01:09
    [Bug] Width-mismatch diagnostic prints the same name for both sides when two constants share a name
  • Pull request#391soronpo2026-05-17 00:08
  • Issue#382soronpo2026-05-16 23:59
    Missing ref error when design parameter default uses global CONST values
  • Pull request#390soronpo2026-05-16 23:59
  • Pull request#390soronpo2026-05-16 23:44
  • Pull request#377scala-steward2026-04-07 16:20
  • Issue#372soronpo2026-04-06 09:30
    Unreadable error messages when calling nonexistent methods on DFHDL types
  • Issue#371soronpo2026-04-06 09:30
    [Bug] Inline conditional '<>' generates non-procedural if statement in SV output
  • Issue#369soronpo2026-04-06 09:30
    [Bug/Feature] DFHDL generates unique module names (mandelbrot_0/1/2/3) for identical parameterized instances instead of reusing one module
  • Issue#370soronpo2026-04-06 09:30
    [Bug] Compiler generates bare '0' literal between wire declarations in SV output
  • Issue comment#369soronpo2026-04-05 02:20
    [Bug/Feature] DFHDL generates unique module names (mandelbrot_0/1/2/3) for identical parameterized instances instead of reusing one module
  • Issue#370soronpo2026-04-04 13:29
    [Bug] Compiler generates bare '0' literal between wire declarations in SV output
  • Issue#353soronpo2026-04-04 02:30
    [Bug] Assertion failure when using .bits.sint conversion in clocked process
  • Issue#364soronpo2026-04-04 02:29
    [Bug] Assertion error when using parameterized Int <> CONST in sd"..." signed decimal interpolator
  • Issue#366soronpo2026-04-04 02:29
    [Bug] sd"...'value" with DFHDL Int <> CONST parameter generates unsigned literal
  • Pull request#368soronpo2026-04-04 02:14
  • Issue comment#363soronpo2026-04-04 01:33
    [Bug] SInt.bits(hi, lo) generates {signal}[hi:lo] with redundant braces that Yosys fails to parse
  • Issue#358soronpo2026-04-04 01:26
    [Bug] cav hierarchical verification: blackboxed child modules prevent sequential state proof in parent
  • Issue comment#358soronpo2026-04-04 01:26
    [Bug] cav hierarchical verification: blackboxed child modules prevent sequential state proof in parent
  • Issue comment#365soronpo2026-04-04 01:26
    [Bug] cav script: original.sv detected as child module causing re-definition error in Yosys
  • Issue comment#354soronpo2026-04-04 01:19
    [Bug] Parametric bit-slice rbits(FBITS-2, 0) generates rbits[FBITS-1:0] instead of rbits[FBITS-2:0]
  • Issue#366soronpo2026-04-03 16:31
    [Bug] sd"...'value" with DFHDL Int <> CONST parameter generates unsigned literal
  • Issue#361soronpo2026-04-03 13:30
    [Bug] cav script includes original.sv in gate read causing module re-definition error
  • Issue#352soronpo2026-03-31 03:49
    [Bug] Generated typedef enum missing base type — defaults to 32-bit int

Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 26 stars here means stars gained during the window, not the repo's star count.