Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and multi cycle instructions, ALU unit works in parallel with a multiplication unit, and Reorder Buffer to guarantee in-order termination.
active 2024-02-09 → 2025-02-17 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 375 days from 2024-02-09 to 2025-02-17. Pushes: 6 total, peak 6 in a day. Pull requests: 3 total, peak 2 in a day. Issues: 0 total, peak 0 in a day. Comments: 6 total, peak 3 in a day. Stars: 13 total, peak 3 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| oharboe | 7 | 0 | 2 | 5 |
| EngAhmed21 | 6 | 6 | 0 | 0 |
| jrrk2 | 2 | 0 | 1 | 1 |
Recent activity
Latest issues, pull requests and releases
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 13 stars here means stars gained during the window, not the repo's star count.