IteratorandIterator/A-MIPS-processor-that-is-compiler-friendly
View on GitHub ↗Related repositories →The MIPS processor features a pipelined structure, supports serial communication, and can utilize the SRAM resources on the FPGA development board. It implements 56 instructions, supports delay slots, and can run successfully on an FPGA development board with a clock frequency of 80MHz.
active 2023-10-31 → 2023-12-17 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 48 days from 2023-10-31 to 2023-12-17. Pushes: 5 total, peak 4 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| IteratorandIterator | 5 | 5 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.