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KaranpreetRaja/Verilog-RISC-V-Processor

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active 2024-11-152024-11-28 (UTC)

Partial coverage25,518 / 26,320 hourly files (97%) · 2 absent upstream · 801 failed, retryable2023-08-152026-08-15 (UTC)— sampled evenly across the window, so rankings and trends hold; absolute counts scale up.
Events
36
Pushes
16
Pull requests
2
Issues
0
Stars
0
Forks
0

Activity over time

Daily event counts in the loaded window

Line chart, 14 days from 2024-11-15 to 2024-11-28. Pushes: 16 total, peak 4 in a day. Pull requests: 2 total, peak 1 in a day. Issues: 0 total, peak 0 in a day. Comments: 1 total, peak 1 in a day. Stars: 0 total, peak 0 in a day.

  • Pushes
  • Pull requests
  • Issues
  • Comments
  • Stars

Top contributors

Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity

ContributorContributionsPushesPRsComments
icabuent7700
salwan-aldhahab7520
quardinlyttle6301
KaranpreetRaja2100

Recent activity

Latest issues, pull requests and releases

  • Pull request#1salwan-aldhahab2024-11-28 23:30
  • Pull request#1salwan-aldhahab2024-11-15 05:11

Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.