Skip to content

A Chisel3 package to describe verilog FPGA template and macro for hardened FPGA modules

active 2023-12-02 → 2024-12-19 (UTC)

Complete coverage28,136 / 28,136 hourly files (100%) · 2 absent upstream2023-08-15 → 2026-10-30 (UTC)
Events
34
Pushes
11
Pull requests
6
Issues
0
Stars
0
Forks
0

Activity over time

Daily event counts in the loaded window

Line chart, 384 days from 2023-12-02 to 2024-12-19. Pushes: 11 total, peak 5 in a day. Pull requests: 6 total, peak 2 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.

  • Pushes
  • Pull requests
  • Issues
  • Comments
  • Stars

Top contributors

Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity

ContributorContributionsPushesPRsComments
Martoni151140
Kev-J2020

Recent activity

Latest issues, pull requests and releases

  • Releasev6.2.2Martoni2024-12-19 08:13
  • Release6.2.0Martoni2024-12-19 08:13
  • Pull request#13Martoni2024-12-19 08:12
  • Pull request#13Kev-J2024-12-18 10:09
  • Releasev6.2.2Martoni2024-12-02 09:15
  • Pull request#12Martoni2024-12-02 09:13
  • Pull request#12Kev-J2024-11-29 14:14
  • Releasev6.2.1Martoni2024-03-07 21:12
  • Releasev6.2.0Martoni2024-03-07 21:08
  • Release6.1.0Martoni2024-03-07 11:49
  • Pull request#11Martoni2024-03-07 11:45
  • Pull request#11Martoni2024-03-07 11:45
  • Releasev6.1.0Martoni2024-03-07 11:44

Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.