Welcome to the 5-Stage Pipeline RV32I Processor repository! This project implements a RISC-V 32-bit processor with a classic 5-stage pipeline architecture using Chisel. The processor is designed to handle instruction fetch, decode, execute, memory access, and write-back stages efficiently.
active 2025-01-18 → 2025-01-18 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 1 days from 2025-01-18 to 2025-01-18. Pushes: 6 total, peak 6 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| Meowwww5 | 6 | 6 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.