This repository contains the Verilog code and testbench for a First-In-First-Out (FIFO) memory module. The FIFO memory structure stores and retrieves data elements in the order they were added, using two internal pointers to track the write and read positions.
active 2024-08-07 → 2025-02-22 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 200 days from 2024-08-07 to 2025-02-22. Pushes: 4 total, peak 3 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 1 total, peak 1 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| MohamedHussein27 | 4 | 4 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 1 stars here means stars gained during the window, not the repo's star count.