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透過數位邏輯結合VHDL與Verilog的過程,作為從基礎數位邏輯到計算機系統結構,並實作出一顆CPU的教學書籍,希望未來可以成為教學範例檔案。目前將開發轉移到GitLab,因為可以呈現數學與MUL圖。

active 2023-09-012025-09-22 (UTC)

Complete coverage26,359 / 26,359 hourly files (100%) · 2 absent upstream2023-08-152026-08-17 (UTC)
Events
26
Pushes
7
Pull requests
0
Issues
0
Stars
14
Forks
2

Activity over time

Daily event counts in the loaded window

Line chart, 753 days from 2023-09-01 to 2025-09-22. Pushes: 7 total, peak 6 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 14 total, peak 1 in a day.

  • Pushes
  • Pull requests
  • Issues
  • Comments
  • Stars

Stars, PRs, issues and forks are under-captured in the later part of this window. GH Archive progressively stopped capturing non-push events during 2026 — −95% or worse by the end of the window. Every series here except Pushes fades for that reason, so a decline above reflects the archive, not this repository. Pushes stay reliable throughout, so read them, and the contributor counts derived from them, as the real signal. Data health has the measurements.

Top contributors

Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity

ContributorContributionsPushesPRsComments
timmy611097700

Recent activity

Latest issues, pull requests and releases

No issue or PR events — this repo's activity is pushes only.

Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 14 stars here means stars gained during the window, not the repo's star count.