This project focuses on simulating the behavior and performance of a simple Ethernet protocol implementation using Verilog RTL design. The simulation aims to evaluate the protocol's functionality, analyze its performance under various conditions, and identify any potential bottlenecks or issues.
active 2024-03-09 → 2024-03-11 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 3 days from 2024-03-09 to 2024-03-11. Pushes: 6 total, peak 5 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| Phaneendra488 | 6 | 6 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.