CRC-3 Module with Latch-Based Clock Gating for Tiny Tape out . A compact 1x1 tile chip design implementing a CRC-3 error detection system using a 3-bit LFSR and latch-based clock gating for power efficiency. Part of the Tiny Tapeout TT07 initiative, this Verilog project optimizes for minimal area and energy use.
active 2025-09-07 → 2025-09-07 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 1 days from 2025-09-07 to 2025-09-07. Pushes: 22 total, peak 22 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Stars, PRs, issues and forks are under-captured in the later part of this window. GH Archive progressively stopped capturing non-push events during 2026 — −95% or worse by the end of the window. Every series here except Pushes fades for that reason, so a decline above reflects the archive, not this repository. Pushes stay reliable throughout, so read them, and the contributor counts derived from them, as the real signal. Data health has the measurements.
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| PrajwalM28 | 22 | 22 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.