This project implements a 5-stage pipelined MIPS32 processor in Verilog, simulating the fetch, decode, execute, memory, and write-back stages. A testbench validates correct execution of arithmetic, logical, and control-flow instructions, as well as register and memory operations.
active 2025-01-18 → 2025-01-18 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 1 days from 2025-01-18 to 2025-01-18. Pushes: 9 total, peak 9 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| PyCoder369 | 9 | 9 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.