VHDL / System Verilog to Verilog converter, based on Yosys and the plugins ghdl-yosys-plugin and synlig.
active 2023-09-24 → 2024-12-11 (UTC)
Complete coverage27,400 / 27,400 hourly files (100%) · 2 absent upstream2023-08-15 → 2026-09-29 (UTC)
Events
19
Pushes
8
Pull requests
0
Issues
1
Stars
8
Forks
0
Activity over time
Daily event counts in the loaded window
Line chart, 445 days from 2023-09-24 to 2024-12-11. Pushes: 8 total, peak 2 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 1 total, peak 1 in a day. Comments: 0 total, peak 0 in a day. Stars: 8 total, peak 2 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| rodrigomelo9 | 9 | 8 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 8 stars here means stars gained during the window, not the repo's star count.