Welcome to the "VerilogBasicGatesImplementation" repository! This project showcases the implementation of fundamental digital logic gates using the Verilog hardware description language (HDL). Digital logic gates are the build This repository provides concise Verilog code for commonly used gates such as AND, OR, NOT, NAND, NOR, and XOR.
active 2023-12-16 → 2025-04-26 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 498 days from 2023-12-16 to 2025-04-26. Pushes: 17 total, peak 17 in a day. Pull requests: 1 total, peak 1 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 1 total, peak 1 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Stars, PRs, issues and forks are under-captured in the later part of this window. GH Archive progressively stopped capturing non-push events during 2026 — −95% or worse by the end of the window. Every series here except Pushes fades for that reason, so a decline above reflects the archive, not this repository. Pushes stay reliable throughout, so read them, and the contributor counts derived from them, as the real signal. Data health has the measurements.
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| Sreyz03 | 18 | 17 | 1 | 0 |
Recent activity
Latest issues, pull requests and releases
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 1 stars here means stars gained during the window, not the repo's star count.