In this project, you will be tasked with implementing pipeline registers and connecting all the modules you've created so far to build a complete RISC-V processor. The successful completion of this project will result in a functional MIPS processor, and you'll have the opportunity to gain bonus points by handling hazards.
active 2023-09-24 → 2024-12-30 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 464 days from 2023-09-24 to 2024-12-30. Pushes: 0 total, peak 0 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 8 total, peak 3 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
Nobody pushed, opened or commented here in the loaded window — this repo's activity is stars and forks only.
Recent activity
Latest issues, pull requests and releases
No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 8 stars here means stars gained during the window, not the repo's star count.