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A simple implementation of a UART modem in Verilog.

active 2023-09-032026-04-08 (UTC)

Complete coverage26,673 / 26,673 hourly files (100%) · 2 absent upstream2023-08-152026-08-30 (UTC)
Events
110
Pushes
0
Pull requests
0
Issues
2
Stars
97
Forks
9

Activity over time

Daily event counts in the loaded window

Line chart, 949 days from 2023-09-03 to 2026-04-08. Pushes: 0 total, peak 0 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 2 total, peak 1 in a day. Comments: 2 total, peak 1 in a day. Stars: 97 total, peak 4 in a day.

  • Pushes
  • Pull requests
  • Issues
  • Comments
  • Stars

Stars, PRs, issues and forks are under-captured in the later part of this window. GH Archive progressively stopped capturing non-push events during 2026 — −95% or worse by the end of the window. Every series here except Pushes fades for that reason, so a decline above reflects the archive, not this repository. Pushes stay reliable throughout, so read them, and the contributor counts derived from them, as the real signal. Data health has the measurements.

Top contributors

Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity

ContributorContributionsPushesPRsComments
m1geo1001
mayank-kabra20011000
CHENfd5151000
Abhay123kumar1001

Recent activity

Latest issues, pull requests and releases

  • Issue#7CHENfd5152024-11-14 12:48
    A small modification
  • Issue comment#6m1geo2024-10-19 18:05
    Synthesis testing failed.
  • Issue#6mayank-kabra20012023-09-05 11:48
    Synthesis testing failed.

Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 97 stars here means stars gained during the window, not the repo's star count.