This project implements basic RAM and ROM memory modules using Verilog. It includes the simulation and verification of memory read and write operations for RAM and the preloaded data functionality for ROM.
active 2025-01-17 → 2025-01-18 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 2 days from 2025-01-17 to 2025-01-18. Pushes: 14 total, peak 10 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 1 total, peak 1 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| blessyjeba10c | 14 | 14 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 1 stars here means stars gained during the window, not the repo's star count.