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drserafin/Lab-4-VHDL-Structural-Modeling

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The main purpose of this lab project is to help students learn how to construct and implement the architecture of a digital system’s entities that are based on structural modeling process

active 2024-04-162024-05-06 (UTC)

Complete coverage26,647 / 26,647 hourly files (100%) · 2 absent upstream2023-08-152026-08-29 (UTC)
Events
22
Pushes
15
Pull requests
0
Issues
2
Stars
0
Forks
0

Activity over time

Daily event counts in the loaded window

Line chart, 21 days from 2024-04-16 to 2024-05-06. Pushes: 15 total, peak 11 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 2 total, peak 1 in a day. Comments: 1 total, peak 1 in a day. Stars: 0 total, peak 0 in a day.

  • Pushes
  • Pull requests
  • Issues
  • Comments
  • Stars

Top contributors

Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity

ContributorContributionsPushesPRsComments
drserafin181501

Recent activity

Latest issues, pull requests and releases

  • Issue comment#2drserafin2024-05-06 16:55
    Q2) Design an 8 channel Switching Unit
  • Issue#2drserafin2024-05-06 16:48
    Q2) Design an 8 channel Switching Unit
  • Issue#1drserafin2024-04-16 01:27
    image of question #1

Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.