Skip to content

LEC - Logic Equivalence Checking - Formal Verification

active 2025-11-132026-08-20 (UTC)

Complete coverage26,780 / 26,780 hourly files (100%) · 2 absent upstream2023-08-152026-09-03 (UTC)
Events
455
Pushes
343
Pull requests
61
Issues
5
Stars
14
Forks
1

Activity over time

Daily event counts in the loaded window

Line chart, 281 days from 2025-11-13 to 2026-08-20. Pushes: 343 total, peak 17 in a day. Pull requests: 61 total, peak 8 in a day. Issues: 5 total, peak 2 in a day. Comments: 19 total, peak 2 in a day. Stars: 14 total, peak 3 in a day.

  • Pushes
  • Pull requests
  • Issues
  • Comments
  • Stars

Stars, PRs, issues and forks are under-captured in the later part of this window. GH Archive progressively stopped capturing non-push events during 2026 — −95% or worse by the end of the window. Every series here except Pushes fades for that reason, so a decline above reflects the archive, not this repository. Pushes stay reliable throughout, so read them, and the contributor counts derived from them, as the real signal. Data health has the measurements.

Top contributors

Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity

ContributorContributionsPushesPRsComments
nanocoh406345601
codecov[bot]150015
xtofalex4000
jhkim-pii3002
oharboe2020
maliberty1001

Recent activity

Latest issues, pull requests and releases

  • Pull request#148nanocoh2026-07-06 13:39
  • Pull request#131nanocoh2026-04-24 00:05
  • Issue comment#129codecov[bot]2026-04-16 09:29
    naja update
  • Pull request#126nanocoh2026-04-12 13:03
  • Pull request#124nanocoh2026-04-10 00:05
  • Issue comment#121nanocoh2026-04-08 13:22
    Relax rules on Liberty file naming?
  • Pull request#122nanocoh2026-04-08 09:07
  • Issue#120xtofalex2026-04-08 08:32
    kepler-formal can't find port in Liberty bundle statement
  • Issue comment#106jhkim-pii2026-03-16 01:33
    Is it possible to input multiple Verilog files for a single design instead of a single integrated Verilog file?
  • Issue comment#106jhkim-pii2026-03-14 10:44
    Is it possible to input multiple Verilog files for a single design instead of a single integrated Verilog file?
  • Pull request#107oharboe2026-03-13 15:03
  • Issue#104jhkim-pii2026-03-11 12:10
    `Seed output term is not a single driver` error on top-level inout port
  • Pull request#103oharboe2026-03-10 22:26
  • Issue#99xtofalex2026-03-04 07:19
    Liberty parser error when bus has no bus-level `direction` attribute
  • Pull request#96nanocoh2026-03-03 23:12
  • Issue comment#96codecov[bot]2026-02-27 22:58
    Fix for non continues truth tables
  • Pull request#98nanocoh2026-02-27 22:38
  • Pull request#91nanocoh2026-02-19 23:56
  • Pull request#91nanocoh2026-02-19 17:16
  • Pull request#88nanocoh2026-02-15 00:46
  • Issue comment#88codecov[bot]2026-02-15 00:21
    MT safe convert in t2be
  • Issue comment#85codecov[bot]2026-02-05 21:54
    cleaning
  • Pull request#84nanocoh2026-02-05 13:40
  • Issue comment#84codecov[bot]2026-02-05 13:25
    build primary points fix
  • Pull request#83nanocoh2026-01-23 13:14

Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 14 stars here means stars gained during the window, not the repo's star count.