One of the labs from my digital circuits class in which we created 2 types of stacks in Verilog: FIFO and LIFO. Both stacks are read-first, but the FIFO is a circular stack whereas the LIFO is not. Both modules also come with an associated testbench to verify that they work: FIFO_tb and LIFO_tb
active 2023-11-03 → 2023-11-03 (UTC)
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Line chart, 1 days from 2023-11-03 to 2023-11-03. Pushes: 3 total, peak 3 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.
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| Contributor | Contributions | Pushes | PRs | Comments |
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| locks645 | 3 | 3 | 0 | 0 |
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