Testchip implementation of the CROSS and LESS algorithms with custom hardware accelerators integrated into the Ibex 32 bit RISC-V CPU core.
SystemVerilog · active 2025-03-02 → 2026-06-28 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 484 days from 2025-03-02 to 2026-06-28. Pushes: 37 total, peak 3 in a day. Pull requests: 42 total, peak 2 in a day. Issues: 29 total, peak 3 in a day. Comments: 134 total, peak 12 in a day. Stars: 164 total, peak 3 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Stars, PRs, issues and forks are under-captured in the later part of this window. GH Archive progressively stopped capturing non-push events during 2026 — −95% or worse by the end of the window. Every series here except Pushes fades for that reason, so a decline above reflects the archive, not this repository. Pushes stay reliable throughout, so read them, and the contributor counts derived from them, as the real signal. Data health has the measurements.
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| marnovandermaas | 40 | 0 | 4 | 23 |
| mndstrmr | 31 | 15 | 1 | 6 |
| rswarbrick | 27 | 0 | 1 | 15 |
| SamuelRiedel | 27 | 0 | 3 | 16 |
| nasahlpa | 21 | 0 | 5 | 7 |
| github-merge-queue[bot] | 20 | 20 | 0 | 0 |
| hcallahan-lowrisc | 19 | 0 | 1 | 10 |
| vogelpi | 17 | 0 | 0 | 7 |
| akashlevy | 11 | 0 | 2 | 7 |
| andreaskurth | 10 | 0 | 3 | 6 |
| elliotb-lowrisc | 8 | 0 | 2 | 5 |
| ZhongYic00 | 6 | 0 | 1 | 2 |
| Timmmm | 5 | 0 | 0 | 2 |
| machshev | 5 | 0 | 0 | 2 |
| Zxis233 | 4 | 0 | 0 | 3 |
| JesesePU | 4 | 0 | 0 | 0 |
| nbdd0121 | 4 | 0 | 1 | 2 |
| pkkim | 3 | 0 | 3 | 0 |
| ha0lyu | 3 | 0 | 2 | 1 |
| icb-DVcrew | 3 | 0 | 0 | 1 |
Recent activity
Latest issues, pull requests and releases
- Issue#2452jimmymtest2026-06-12 06:12[BUG] Misaligned cross-page `sw` partially writes memory before store fault completes
- Pull request#2449SamuelRiedel2026-06-08 12:59
- Issue comment#2193korran2026-06-08 00:21Pipeline not being flushed on PMP register clears
- Issue comment#2439elliotb-lowrisc2026-05-28 07:10[dv] Add exception handler to CSR test generator (Fixes #1337)
- Pull request#2437hcallahan-lowrisc2026-05-14 07:54
- Issue#2430JesesePU2026-05-13 04:21I Found a $50K Opportunity Hiding in a GitHub Repo
- Issue#2421JesesePU2026-05-12 19:06How TSU's 16 Custom RISC-V Instructions Accelerate AI Infere
- Issue#2417JesesePU2026-05-12 16:28How a 15-Year-Old Could Build the Next Apple Silicon
- Issue#2410JesesePU2026-05-12 03:16How a 15-Year-Old Could Build the Next Apple Silicon
- Issue comment#2398SamuelRiedel2026-04-27 12:07[dv] Add RV32ZC handling to ISA strings
- Issue comment#2390SamuelRiedel2026-04-17 15:54Enforce x0 Register Write Protection in Decoder with Verification Testbench
- Pull request#2378marnovandermaas2026-04-14 11:57
- Pull request#2386Anubhav-302026-04-12 14:07
- Pull request#2376nasahlpa2026-04-09 08:41
- Pull request#2375satnam65022026-04-07 22:00
- Issue comment#2354Zxis2332026-03-14 05:00[syn] Adapt for Yosys 0.60
- Issue#2372mayshajahanroja-spec2026-02-28 15:16Surelog syntax error when parsing ibex_core.f (Syntax error: no viable alternative at input 'ibex_top.',)
- Issue#2372mayshajahanroja-spec2026-02-28 15:16Surelog syntax error when parsing ibex_core.f (Syntax error: no viable alternative at input 'ibex_top.',)
- Pull request#2346SamuelRiedel2026-02-16 13:38
- Pull request#2364nasahlpa2026-02-10 11:59
- Pull request#2367marnovandermaas2026-02-04 12:26
- Pull request#2363nasahlpa2026-02-03 06:28
- Issue#2360hainnkb2026-01-27 08:36PLIC claim process with Ibex
- Issue comment#2355Haouo2026-01-23 02:01[simple_system] UNOPTFLAT Verilator lint waived
- Issue comment#2345marnovandermaas2026-01-20 17:29Problem building the simple system
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 164 stars here means stars gained during the window, not the repo's star count.