In this lab, we were to design a generic Arithmetic Logic Unit circuit and verify the design through simulations and testbenches. For the higher bit ALUs, we were restricted to using structural design concepts and a 1-bit ALU as our foundational building block
active 2023-09-19 → 2023-09-19 (UTC)
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| Contributor | Contributions | Pushes | PRs | Comments |
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| ppatel2612 | 1 | 1 | 0 | 0 |
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