The aim of this project is to demonstrate the working of the RF Data Converter IP by analyzing and replicating a part of the official Xilinx design. The goal is to recreate the radio hierarchy using custom IPs (amplitude controller and packet generator) designed in Vitis HLS 2022.1.
active 2024-08-11 → 2024-08-16 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 6 days from 2024-08-11 to 2024-08-16. Pushes: 3 total, peak 3 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 1 total, peak 1 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| riyasach189 | 3 | 3 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 1 stars here means stars gained during the window, not the repo's star count.