Implementing a two-level (L1 and L2) cache system with configurable parameters such as block size and associativity. Takes memory address trace files as input for precise cache behavior emulation and performance analysis. An invaluable tool for exploring cache configurations and optimizing memory hierarchies for enhanced system performance.
active 2024-01-01 → 2024-01-01 (UTC)
Activity over time
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Line chart, 1 days from 2024-01-01 to 2024-01-01. Pushes: 2 total, peak 2 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.
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Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| rugvedmhatre | 2 | 2 | 0 | 0 |
Recent activity
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No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.