Processor implemented in System Verilog based on RISC-V ISA
active 2023-08-29 → 2023-11-20 (UTC)
Complete coverage26,410 / 26,410 hourly files (100%) · 2 absent upstream2023-08-15 → 2026-08-19 (UTC)
Events
19
Pushes
8
Pull requests
2
Issues
1
Stars
4
Forks
0
Activity over time
Daily event counts in the loaded window
Line chart, 84 days from 2023-08-29 to 2023-11-20. Pushes: 8 total, peak 4 in a day. Pull requests: 2 total, peak 2 in a day. Issues: 1 total, peak 1 in a day. Comments: 0 total, peak 0 in a day. Stars: 4 total, peak 2 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| sh-mug | 11 | 8 | 2 | 0 |
Recent activity
Latest issues, pull requests and releases
- Issue#2sh-mug2023-09-20 15:18Add Unit Tests
- Pull request#1sh-mug2023-09-18 09:19
- Pull request#1sh-mug2023-09-18 09:19
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 4 stars here means stars gained during the window, not the repo's star count.