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simlar-0/risc-v-disassembler

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active 2025-02-052025-06-15 (UTC)

Complete coverage26,581 / 26,581 hourly files (100%) · 2 absent upstream2023-08-152026-08-26 (UTC)
Events
178
Pushes
60
Pull requests
28
Issues
29
Stars
2
Forks
0

Activity over time

Daily event counts in the loaded window

Line chart, 131 days from 2025-02-05 to 2025-06-15. Pushes: 60 total, peak 9 in a day. Pull requests: 28 total, peak 4 in a day. Issues: 29 total, peak 6 in a day. Comments: 9 total, peak 3 in a day. Stars: 2 total, peak 1 in a day.

  • Pushes
  • Pull requests
  • Issues
  • Comments
  • Stars

Stars, PRs, issues and forks are under-captured in the later part of this window. GH Archive progressively stopped capturing non-push events during 2026 — −95% or worse by the end of the window. Every series here except Pushes fades for that reason, so a decline above reflects the archive, not this repository. Pushes stay reliable throughout, so read them, and the contributor counts derived from them, as the real signal. Data health has the measurements.

Top contributors

Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity

ContributorContributionsPushesPRsComments
yuvve8029157
simlar-06831132

Recent activity

Latest issues, pull requests and releases

  • Issue#35yuvve2025-06-01 08:17
    Give option to produce ABI-names instead of register numbers
  • Pull request#36yuvve2025-06-01 08:17
  • Issue#31simlar-02025-04-28 08:14
    Remove special registers from RISC-V-Disassmbler
  • Pull request#32simlar-02025-04-28 08:13
  • Pull request#32simlar-02025-04-27 07:32
  • Issue#31yuvve2025-04-22 13:04
    Remove special registers from RISC-V-Disassmbler
  • Issue#29yuvve2025-03-12 15:49
    Add a struct for each parsed instruction and use them instead of enum fields in ParsedInstruction32
  • Issue comment#30yuvve2025-03-12 15:29
    Refactor ParsedInstruction32 enum variants to structs
  • Pull request#30yuvve2025-03-12 15:13
  • Issue#27simlar-02025-03-12 09:13
    Make SpecialRegister public
  • Pull request#28simlar-02025-03-12 09:13
  • Issue#29yuvve2025-03-12 08:01
    Add a struct for each parsed instruction and use them instead of enum fields in ParsedInstruction32
  • Issue#25simlar-02025-03-12 06:49
    Support endianess in disassembler
  • Pull request#26simlar-02025-03-08 14:42
  • Issue#25yuvve2025-03-05 14:13
    Support endianess in disassembler
  • Issue#23yuvve2025-02-27 14:40
    Implement fmt::Display for the parsed instruction
  • Pull request#24yuvve2025-02-27 14:40
  • Pull request#24yuvve2025-02-27 14:30
  • Issue#23yuvve2025-02-27 14:00
    Implement fmt::Display for the parsed instruction
  • Issue#21yuvve2025-02-19 16:03
    CI for RISC-V disassembler (automatically run tests on PRs and merges to main)
  • Pull request#22yuvve2025-02-19 16:03
  • Issue#19yuvve2025-02-19 16:02
    Add readme to RISC-V disassmebler
  • Pull request#20yuvve2025-02-19 16:02
  • Issue comment#22yuvve2025-02-19 14:06
    Add build and test workflow
  • Pull request#22yuvve2025-02-19 14:05

Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 2 stars here means stars gained during the window, not the repo's star count.