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SystemVerilog IP design & verification

active 2023-08-23 → 2024-07-23 (UTC)

Complete coverage27,797 / 27,797 hourly files (100%) · 2 absent upstream2023-08-15 → 2026-10-16 (UTC)
Events
781
Pushes
348
Pull requests
38
Issues
286
Stars
9
Forks
0

Activity over time

Daily event counts in the loaded window

Line chart, 336 days from 2023-08-23 to 2024-07-23. Pushes: 348 total, peak 28 in a day. Pull requests: 38 total, peak 9 in a day. Issues: 286 total, peak 100 in a day. Comments: 12 total, peak 5 in a day. Stars: 9 total, peak 3 in a day.

  • Pushes
  • Pull requests
  • Issues
  • Comments
  • Stars

Top contributors

Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity

ContributorContributionsPushesPRsComments
foez-ahmed32814921
foez-ahmed-8041293142279
mdrazuahamed645281
Reyad0710411
github-actions[bot]1100
Shahid-Uddin-Ahmed1000

Recent activity

Latest issues, pull requests and releases

Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 9 stars here means stars gained during the window, not the repo's star count.