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RISC-V CPU with PMU

active 2025-11-112026-02-11 (UTC)

Complete coverage26,573 / 26,573 hourly files (100%) · 2 absent upstream2023-08-152026-08-26 (UTC)
Events
110
Pushes
22
Pull requests
11
Issues
4
Stars
27
Forks
17

Activity over time

Daily event counts in the loaded window

Line chart, 93 days from 2025-11-11 to 2026-02-11. Pushes: 22 total, peak 4 in a day. Pull requests: 11 total, peak 3 in a day. Issues: 4 total, peak 2 in a day. Comments: 14 total, peak 2 in a day. Stars: 27 total, peak 4 in a day.

  • Pushes
  • Pull requests
  • Issues
  • Comments
  • Stars

Stars, PRs, issues and forks are under-captured in the later part of this window. GH Archive progressively stopped capturing non-push events during 2026 — −95% or worse by the end of the window. Every series here except Pushes fades for that reason, so a decline above reflects the archive, not this repository. Pushes stay reliable throughout, so read them, and the contributor counts derived from them, as the real signal. Data health has the measurements.

Top contributors

Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity

ContributorContributionsPushesPRsComments
jserv4722011
jgw09155032
eastWillow4011
yushengtzou3030
n261418762020
MP4ZA1010
Ten-tw1000
jin111091000
Jackiempty1010

Recent activity

Latest issues, pull requests and releases

  • Pull request#18jgw09152026-02-11 08:29
  • Issue comment#13jserv2026-01-31 14:42
    Feature fall stall prevention in pipeline CPUs
  • Pull request#17jgw09152026-01-29 07:29
  • Issue comment#13jgw09152026-01-21 06:17
    Feat/ Fall stall prevention in pipeline CPUs
  • Pull request#16yushengtzou2026-01-21 04:36
  • Pull request#16yushengtzou2026-01-21 04:27
  • Issue comment#15jserv2026-01-21 03:46
    Docs: fix typo in InstructionDecode.scala
  • Pull request#15yushengtzou2026-01-21 03:46
  • Issue comment#11jserv2026-01-03 13:01
    Sync with upstream and keep stage 1 to 3 of pipeline CPU
  • Pull request#11MP4ZA2026-01-03 12:57
  • Pull request#8jgw09152025-12-26 05:45
  • Issue comment#8jserv2025-12-26 03:01
    Fix/false load-use stall by gating rs1 amd rs2 hazard check
  • Issue comment#8jgw09152025-12-26 02:59
    Fix/false load-use stall by gating rs1 amd rs2 hazard check
  • Issue#9jserv2025-12-25 19:17
    4-soc: Missing sim.cpp in verilog/verilator directory
  • Issue#9Ten-tw2025-12-25 18:11
    4-soc: Missing sim.cpp in verilog/verilator directory
  • Pull request#7n261418762025-12-07 07:55
  • Pull request#7n261418762025-12-07 07:55
  • Issue comment#6jserv2025-12-07 02:30
    Refactor PipelineRegister to simplify logic
  • Issue#4jserv2025-12-06 03:45
    Incompatibility of "timeout" command on MacOS
  • Pull request#5Jackiempty2025-12-06 03:45
  • Pull request#3eastWillow2025-12-04 16:16
  • Issue comment#2jserv2025-11-28 02:10
    Improve RISC-V toolchain detection
  • Issue comment#1jserv2025-11-26 11:52
    make check-deps passes, but make compliance still fails due to missing RISC-V toolchain
  • Issue#1jin111092025-11-26 10:41
    make check-deps passes, but make compliance still fails due to missing RISC-V toolchain

Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 27 stars here means stars gained during the window, not the repo's star count.