Circuit IR Compilers and Tools
active 2026-01-16 → 2026-03-06 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 50 days from 2026-01-16 to 2026-03-06. Pushes: 241 total, peak 186 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 5 total, peak 3 in a day. Comments: 14 total, peak 7 in a day. Stars: 8 total, peak 4 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Stars, PRs, issues and forks are under-captured in the later part of this window. GH Archive progressively stopped capturing non-push events during 2026 — −95% or worse by the end of the window. Every series here except Pushes fades for that reason, so a decline above reflects the archive, not this repository. Pushes stay reliable throughout, so read them, and the contributor counts derived from them, as the real signal. Data health has the measurements.
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| thomasnormal | 252 | 233 | 0 | 14 |
| github-actions[bot] | 8 | 8 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
- Issue comment#18thomasnormal2026-03-03 22:49Reduce simulation startup time (E4-E6 optimization phases)
- Issue comment#74thomasnormal2026-03-03 19:51[circt-sim] OBJTN_ZERO regression: 17624bdf8 fix incomplete — 11 UVM lessons still failing
- Issue comment#74thomasnormal2026-03-03 19:35[circt-sim] OBJTN_ZERO regression: 17624bdf8 fix incomplete — 11 UVM lessons still failing
- Issue comment#21thomasnormal2026-03-03 19:01[circt-sim][UVM] run_phase cleanup deadlock: simulation hangs after all objections dropped
- Issue comment#72thomasnormal2026-03-03 16:10[circt-sim] sv/fsm regression: rdata=x after 3d72a82a4 zero-delay drive semantics change
- Issue#9thomasnormal2026-03-03 06:57[ImportVerilog] $bits() on hierarchical reference to parameterized port fails — "unknown hierarchical name"
- Issue#9thomasnormal2026-03-03 06:51[ImportVerilog] $bits() on hierarchical reference to parameterized port fails — "unknown hierarchical name"
- Issue comment#9thomasnormal2026-03-03 06:51[ImportVerilog] $bits() on hierarchical reference to parameterized port fails — "unknown hierarchical name"
- Issue comment#21thomasnormal2026-03-03 06:51[circt-sim][UVM] run_phase cleanup deadlock: simulation hangs after all objections dropped
- Issue#70thomasnormal2026-03-03 05:48[wasm] Build fails on origin/main @ af7b16493: two missing declarations block circt-sim WASM compile
- Issue comment#21thomasnormal2026-03-02 23:24[circt-sim][UVM] run_phase cleanup deadlock: simulation hangs after all objections dropped
- Issue#69thomasnormal2026-03-02 21:59[circt-sim][UVM] Inline constraint randomize() with {…} ignored — values generated outside specified range
- Issue comment#69thomasnormal2026-03-02 21:59[circt-sim][UVM] Inline constraint randomize() with {…} ignored — values generated outside specified range
- Issue#68thomasnormal2026-03-02 21:39Regression in 08646e718: uvm_reg compilation Aborted() in WaitEventOpConversion
- Issue comment#68thomasnormal2026-03-02 21:39Regression in 08646e718: uvm_reg compilation Aborted() in WaitEventOpConversion
- Issue comment#14thomasnormal2026-03-02 17:45[ImportVerilog] Aborted() compiling UVM driver with virtual interface in separate file (multi-file --single-unit)
- Issue comment#22thomasnormal2026-03-02 15:23[ImportVerilog] Class-level constraints ignored during plain randomize() (partial fix of #11)
- Issue comment#21thomasnormal2026-03-02 13:47[circt-sim][UVM] run_phase cleanup deadlock: simulation hangs after all objections dropped
- Issue comment#9thomasnormal2026-03-02 13:45[ImportVerilog] $bits() on hierarchical reference to parameterized port fails — "unknown hierarchical name"
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 8 stars here means stars gained during the window, not the repo's star count.