UVM 1.2 port to Python
active 2023-08-26 → 2026-05-06 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 985 days from 2023-08-26 to 2026-05-06. Pushes: 10 total, peak 6 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 14 total, peak 4 in a day. Comments: 19 total, peak 3 in a day. Stars: 41 total, peak 2 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Stars, PRs, issues and forks are under-captured in the later part of this window. GH Archive progressively stopped capturing non-push events during 2026 — −95% or worse by the end of the window. Every series here except Pushes fades for that reason, so a decline above reflects the archive, not this repository. Pushes stay reliable throughout, so read them, and the contributor counts derived from them, as the real signal. Data health has the measurements.
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| tpoikela | 28 | 10 | 0 | 12 |
| sbhutada | 8 | 0 | 0 | 4 |
| 717-yq | 3 | 0 | 0 | 1 |
| M0stafaRady | 2 | 0 | 0 | 1 |
| AnhHonag | 1 | 0 | 0 | 0 |
| SikoVerilog | 1 | 0 | 0 | 1 |
Recent activity
Latest issues, pull requests and releases
- Issue comment#26tpoikela2025-02-09 13:36registers/vertical_reuse blk-level simulation fails with ghdl/VHDL DUT
- Issue#26tpoikela2025-02-09 13:36registers/vertical_reuse blk-level simulation fails with ghdl/VHDL DUT
- Issue#47tpoikela2025-02-09 13:35Is there a way to mix SystemVerilog UVM and UVM-Python environments?
- Issue#51tpoikela2025-02-09 13:35Do you support uvm_component_param_utils? Any alternative approach? Any example?
- Issue comment#53tpoikela2025-02-09 13:34It seems there are some problems in starting the sequence by using the way of UVMConfigDb.set(self, "xxx.xxx_vsqr.main_phase", "default_sequence", self.vseq ).
- Issue#53tpoikela2025-02-09 13:34It seems there are some problems in starting the sequence by using the way of UVMConfigDb.set(self, "xxx.xxx_vsqr.main_phase", "default_sequence", self.vseq ).
- Issue#54AnhHonag2024-08-26 02:33How to generate file dumpwave by code uvm-python?
- Issue comment#53tpoikela2024-08-24 08:20It seems there are some problems in starting the sequence by using the way of UVMConfigDb.set(self, "xxx.xxx_vsqr.main_phase", "default_sequence", self.vseq ).
- Issue#52717-yq2024-04-19 02:05how should I use the force function in the UVM-Python verification environment, or is there a similar function to force in UVM-Python?
- Issue comment#52717-yq2024-04-19 02:05how should I use the force function in the UVM-Python verification environment, or is there a similar function to force in UVM-Python?
- Issue#52717-yq2024-04-17 03:29how should I use the force function in the UVM-Python verification environment, or is there a similar function to force in UVM-Python?
- Issue#48tpoikela2024-03-17 15:00Should we use PyVSC with UVM-Python to get constrained random and coverage working? Or, is there something similar already in the library?
- Issue#49tpoikela2024-03-17 14:59Any example that shows integrating C++/SystemC predictor?
- Issue comment#50tpoikela2024-03-17 14:57examples/sv is failing ... any ideas?
- Issue comment#51tpoikela2024-02-18 11:09Do you support uvm_component_param_utils? Any alternative approach? Any example?
- Issue comment#51sbhutada2024-02-14 23:47Do you support uvm_component_param_utils? Any alternative approach? Any example?
- Issue comment#51tpoikela2024-02-14 20:26Do you support uvm_component_param_utils? Any alternative approach? Any example?
- Issue#50sbhutada2024-01-13 04:30examples/sv is failing ... any ideas?
- Issue comment#49tpoikela2024-01-10 06:30Any example that shows integrating C++/SystemC predictor?
- Issue comment#48tpoikela2024-01-06 10:59Should we use PyVSC with UVM-Python to get constrained random and coverage working? Or, is there something similar already in the library?
- Issue#48sbhutada2024-01-05 19:31Should we use PyVSC with UVM-Python to get constrained random and coverage working? Or, is there something similar already in the library?
- Issue comment#47sbhutada2024-01-05 19:24Is there a way to mix SystemVerilog UVM and UVM-Python environments?
- Issue comment#47tpoikela2024-01-05 19:17Is there a way to mix SystemVerilog UVM and UVM-Python environments?
- Issue comment#45M0stafaRady2024-01-01 11:24uvm_do doesn't work
- Issue#45M0stafaRady2024-01-01 11:24uvm_do doesn't work
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 41 stars here means stars gained during the window, not the repo's star count.