RISC-V with Direct-Mapped Cache is a digital design project that integrates a single-cycle RISC-V processor with a direct-mapped cache memory system. This repository provides a comprehensive solution for implementing and testing a RISC-V processor combined with a cache to enhance data access efficiency and performance.
active 2024-08-08 → 2024-08-08 (UTC)
Activity over time
Daily event counts in the loaded window
Line chart, 1 days from 2024-08-08 to 2024-08-08. Pushes: 1 total, peak 1 in a day. Pull requests: 0 total, peak 0 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.
- Pushes
- Pull requests
- Issues
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- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| waleedemadyaya | 1 | 1 | 0 | 0 |
Recent activity
Latest issues, pull requests and releases
No issue or PR events — this repo's activity is pushes only.
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.