A simple 8-bit single-cycle processor with a memory sub-system designed using Verilog HDL.
active 2024-06-13 → 2024-07-13 (UTC)
Complete coverage26,551 / 26,551 hourly files (100%) · 2 absent upstream2023-08-15 → 2026-08-25 (UTC)
Events
22
Pushes
10
Pull requests
4
Issues
0
Stars
0
Forks
2
Activity over time
Daily event counts in the loaded window
Line chart, 31 days from 2024-06-13 to 2024-07-13. Pushes: 10 total, peak 7 in a day. Pull requests: 4 total, peak 2 in a day. Issues: 0 total, peak 0 in a day. Comments: 0 total, peak 0 in a day. Stars: 0 total, peak 0 in a day.
- Pushes
- Pull requests
- Issues
- Comments
- Stars
Top contributors
Pushes, PRs, issues, reviews and comments — stars and forks excluded, so this is contribution rather than popularity
| Contributor | Contributions | Pushes | PRs | Comments |
|---|---|---|---|---|
| wethmiranasinghe | 12 | 10 | 2 | 0 |
| Chama28228 | 2 | 0 | 2 | 0 |
Recent activity
Latest issues, pull requests and releases
- Pull request#2wethmiranasinghe2024-06-18 11:47
- Pull request#2Chama282282024-06-18 09:27
- Pull request#1wethmiranasinghe2024-06-14 04:31
- Pull request#1Chama282282024-06-14 04:29
Totals cover only the window loaded into ClickHouse and count events, not GitHub's lifetime totals — 0 stars here means stars gained during the window, not the repo's star count.