youzi27

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active 2023-08-23 → 2026-10-31 (UTC) · 54 repositories

Complete coverage28,376 / 28,376 hourly files (100%) · 2 absent upstream2023-08-15 → 2026-11-09 (UTC)

Events

389

Pushes

112

Pull requests

Issues

108

Reviews

Repositories

Activity over time

Daily event counts in the loaded window

Pushes
Pull requests
Issues

Pull requests and issues are under-captured in the later part of this window. GH Archive progressively stopped recording non-push events during 2026 — −95% or worse by the end of the window. A decline in those two series reflects the archive rather than this account. Pushes stay reliable throughout, so read them as the real signal. Data health has the measurements.

Repositories worked on

Ranked by contributions — pushes, PRs, issues, reviews and comments, so stars and forks do not inflate the list · top 50

Repository	Contributions	Pushes	PRs	Issues	Comments	Last seen
OpenXiangShan/XiangShan	62	0	0	30	32	2026-10-05
youzi27/youzi27.github.io	54	54	0	0	0	2026-09-15
OSCPU/NutShell	39	0	2	32	5	2025-09-26
openhwgroup/cva6	38	0	5	13	20	2025-01-03
riscv-software-src/riscv-isa-sim	29	0	2	10	17	2024-04-18
In2Sec/DiveFuzz	15	15	0	0	0	2026-01-08
OpenXiangShan/NEMU	10	0	0	8	2	2025-11-29
comsec-group/cascade-artifacts	9	0	1	3	5	2024-03-25
ra4ing/DiveFuzz	9	9	0	0	0	2025-12-30
youzi27/cascade-meta	8	8	0	0	0	2024-06-12
openhwgroup/cvfpu	8	0	0	4	4	2024-09-06
cascade-artifacts-designs/cascade-meta	5	0	2	0	3	2024-06-12
chipsalliance/rocket-chip	5	0	0	2	3	2023-12-14
youzi27/cva6	4	4	0	0	0	2026-09-28
youzi27/guozihui.github.io	4	4	0	0	0	2025-08-25
In2Sec/riscv-isa-sim-adapter	4	4	0	0	0	2026-04-10
youzi27/modern-resume-theme	4	4	0	0	0	2025-08-26
youzi27/fpu_div_sqrt_mvp	3	3	0	0	0	2024-04-22
riscv-boom/riscv-boom	3	0	0	2	1	2024-04-23
youzi27/riscv-isa-sim	2	2	0	0	0	2025-08-25
youzi27/NutShell	2	2	0	0	0	2025-12-02
OpenXiangShan/difftest	2	0	0	1	1	2023-12-01
pulp-platform/fpu_div_sqrt_mvp	2	0	1	1	0	2024-04-22
ha0lyu/ChipFuzz	2	0	1	0	1	2025-12-04
youzi27/ChipFuzz	1	1	0	0	0	2025-12-04
ucb-bar/gemmini	1	0	0	1	0	2026-10-31
SonalPinto/kronos	1	0	0	1	0	2024-03-26
youzi27/XiangShan	1	1	0	0	0	2025-11-30
youzi27/cascade-artifacts	1	1	0	0	0	2024-03-14
youzi27/rocket-chip	0	0	0	0	0	2025-12-03
youzi27/rfuzz	0	0	0	0	0	2024-07-26
comsec-group/mirtl	0	0	0	0	0	2025-01-10
riscv/riscv-isa-manual	0	0	0	0	0	2023-11-08
compsec-snu/specdoctor	0	0	0	0	0	2023-10-26
sycuricon/MorFuzz	0	0	0	0	0	2023-08-23
resume/resume.github.com	0	0	0	0	0	2025-08-25
comsec-group/hybridift	0	0	0	0	0	2024-07-23
sproogen/modern-resume-theme	0	0	0	0	0	2025-08-26
llvm/circt	0	0	0	0	0	2024-01-03
michael-etzkorn/rocket-chip	0	0	0	0	0	2023-10-23
microsoft/sca-fuzzer	0	0	0	0	0	2024-01-18
YosysHQ/picorv32	0	0	0	0	0	2023-11-16
JJ-Gaisler/riscv-dv	0	0	0	0	0	2023-10-15
xiaolai/everyone-can-use-english	0	0	0	0	0	2024-01-24
comsec-group/milesan-docker	0	0	0	0	0	2025-12-19
youzi27/riscv-dv-addsome	0	0	0	0	0	2023-12-12
JaewonHur/dlbox	0	0	0	0	0	2025-06-11
comsec-group/encarsia	0	0	0	0	0	2025-09-25
cnrv/riscv-soc-book	0	0	0	0	0	2023-11-16
youzi27/redmule	0	0	0	0	0	2026-10-26

Works with

People who contribute to the same repositories, ranked by how many they share · automation excluded, or every account would appear to work with everyone

Contributor	Shared repos	Repositories in common
ha0lyu	7	riscv-boom/riscv-boom OpenXiangShan/difftest riscv-software-src/riscv-isa-sim ha0lyu/ChipFuzz+3
canxin121	6	openhwgroup/cva6 openhwgroup/cvfpu riscv-software-src/riscv-isa-sim chipsalliance/rocket-chip+2
cyyself	6	riscv-boom/riscv-boom OpenXiangShan/difftest riscv-software-src/riscv-isa-sim chipsalliance/rocket-chip+2
flaviens	6	openhwgroup/cva6 cascade-artifacts-designs/cascade-meta riscv-boom/riscv-boom comsec-group/cascade-artifacts+2
poemonsense	6	OpenXiangShan/difftest riscv-software-src/riscv-isa-sim chipsalliance/rocket-chip OpenXiangShan/NEMU+2
zhangkanqi	6	openhwgroup/cva6 riscv-boom/riscv-boom riscv-software-src/riscv-isa-sim In2Sec/DiveFuzz+2
Lemover	5	openhwgroup/cva6 OpenXiangShan/difftest OpenXiangShan/NEMU OpenXiangShan/XiangShan+1
LuLuji04	5	riscv-boom/riscv-boom riscv-software-src/riscv-isa-sim OpenXiangShan/NEMU OpenXiangShan/XiangShan+1
NewPaulWalker	5	OpenXiangShan/difftest riscv-software-src/riscv-isa-sim chipsalliance/rocket-chip OpenXiangShan/NEMU+1
Phantom1003	5	openhwgroup/cva6 riscv-boom/riscv-boom riscv-software-src/riscv-isa-sim chipsalliance/rocket-chip+1
YzhDDDing	5	openhwgroup/cva6 riscv-boom/riscv-boom chipsalliance/rocket-chip SonalPinto/kronos+1
fly-1011	5	openhwgroup/cva6 cascade-artifacts-designs/cascade-meta openhwgroup/cvfpu OpenXiangShan/NEMU+1
ngc7331	5	OpenXiangShan/difftest chipsalliance/rocket-chip OpenXiangShan/NEMU OpenXiangShan/XiangShan+1
wissygh	5	OpenXiangShan/difftest riscv-software-src/riscv-isa-sim chipsalliance/rocket-chip OpenXiangShan/NEMU+1
Anzooooo	4	OpenXiangShan/difftest OpenXiangShan/XiangShan OpenXiangShan/NEMU riscv-software-src/riscv-isa-sim
Donkey-Hao	4	riscv-software-src/riscv-isa-sim OpenXiangShan/XiangShan OpenXiangShan/NEMU cascade-artifacts-designs/cascade-meta
KatCe	4	riscv-boom/riscv-boom openhwgroup/cva6 riscv-software-src/riscv-isa-sim SonalPinto/kronos
SeddonShen	4	ha0lyu/ChipFuzz chipsalliance/rocket-chip OSCPU/NutShell riscv-boom/riscv-boom
Siudya	4	OpenXiangShan/difftest OpenXiangShan/XiangShan OpenXiangShan/NEMU riscv-software-src/riscv-isa-sim
Tang-Haojin	4	OpenXiangShan/difftest chipsalliance/rocket-chip OpenXiangShan/XiangShan OpenXiangShan/NEMU
abejgonzalez	4	chipsalliance/rocket-chip riscv-software-src/riscv-isa-sim ucb-bar/gemmini riscv-boom/riscv-boom
bantierr	4	chipsalliance/rocket-chip OpenXiangShan/XiangShan cascade-artifacts-designs/cascade-meta riscv-boom/riscv-boom
jerryz123	4	chipsalliance/rocket-chip riscv-software-src/riscv-isa-sim ucb-bar/gemmini riscv-boom/riscv-boom
klin02	4	OpenXiangShan/difftest OpenXiangShan/XiangShan OSCPU/NutShell OpenXiangShan/NEMU
lewislzh	4	OpenXiangShan/difftest OpenXiangShan/XiangShan OpenXiangShan/NEMU riscv-software-src/riscv-isa-sim

Counts cover only the window loaded into ClickHouse and count events, not this account's lifetime totals on GitHub.